#include <xen/lib.h>
#include <xen/sched.h>
#include <asm/current.h>
+#include <asm/hvm/vmx/vmx.h>
#include <public/hvm/ioreq.h>
#include <public/hvm/params.h>
vlapic->hw.apic_base_msr = value;
+ vmx_vlapic_msr_changed(vlapic_vcpu(vlapic));
+
HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
"apic base msr is 0x%016"PRIx64, vlapic->hw.apic_base_msr);
}
return -EINVAL;
lapic_info(s);
+
+ vmx_vlapic_msr_changed(v);
+
return 0;
}
vmx_vmcs_exit(v);
}
-static void vmx_check_vlapic_msr(struct vcpu *v)
+void vmx_vlapic_msr_changed(struct vcpu *v)
{
struct vlapic *vlapic = vcpu_vlapic(v);
uint32_t ctl;
if ( !cpu_has_vmx_virtualize_apic_accesses )
return;
+ vmx_vmcs_enter(v);
ctl = __vmread(SECONDARY_VM_EXEC_CONTROL);
ctl &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
if ( !vlapic_hw_disabled(vlapic) &&
(vlapic_base_address(vlapic) == APIC_DEFAULT_PHYS_BASE) )
ctl |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
__vmwrite(SECONDARY_VM_EXEC_CONTROL, ctl);
+ vmx_vmcs_exit(v);
}
static inline int vmx_do_msr_write(struct cpu_user_regs *regs)
break;
case MSR_IA32_APICBASE:
vlapic_msr_set(vcpu_vlapic(v), msr_content);
- vmx_check_vlapic_msr(v);
break;
default:
if ( !long_mode_do_msr_write(regs) )
void vmx_intr_assist(void);
void vmx_do_resume(struct vcpu *);
void set_guest_time(struct vcpu *v, u64 gtime);
+void vmx_vlapic_msr_changed(struct vcpu *v);
/*
* Exit Reasons